Gate dielectrics for deep sub-0.1 μm CMOS

Recent rapid progress of information technology owes very much to that of semiconductor technologies, especially to that of CMOS. However, the downsizing of CMOS devices is now facing severe difficulties for sub-0.1 μm generations because of various expected limitations. For, example, SiO2 has been used almost exclusively as the material for the gate insulator since the first realization of the MOSFET in 1960. Recently, thinning of the gate oxide has proceeded very aggressively and the gate SiO2 film thickness has already plunged into the direct-tunneling regime and reached 2 nm in the product level. Now, further thinning of the gate SiO2 dielectrics is reaching its limits and the development of new gate dielectrics is becoming the most critical issue for the next generations of CMOS circuitry.